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special features ? 1024 bits electrically programmable read- only memory (eprom) communicates with the economy of one signal plus ground ? eprom partitioned into four 256-bit pages for randomly accessing packetized data ? each memory page can be permanently write- protected to prevent tampering ? device is an ?add onl y? memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by superseding an old page in favor of a newly programmed page ? reduces control, address, data, power, and programming signals to a single data pin ? 8-bit family code specifies DS1982 communications requirements to reader ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to +50c ordering information DS1982-f3+ f3 microcan DS1982-f5+ f5 microcan +denotes a lead(pb)-free/rohs-compliant product. examples of accessories ds9096p self-stick adhesive pad ds9101 multi-purpose clip ds9093ra mounting lock ring ds9093f snap-in fob ds9092 i button probe f3 microcan common i button features ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability be cause no two parts are alike ? multidrop controller for microlan ? digital identification and information by momentary contact ? chip-based data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digita l signal at 16.3kbps ? standard 16mm diameter and 1-wire ? protocol ensure compatibility with i button ? family ? button shape is self-ali gning with cup-shaped probes ? durable stainless steel case engraved with registration number withstands harsh environments ? easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage f5 microcan DS1982 1kb add-only i button 19-4891; rev 8/09 i button and 1-wire are registered trademarks of maxim integrated products, inc. page 1 of 24
DS1982 page 2 of 24 i button description the DS1982 1kb add-only i button is a rugged read/write data carrier that identifies and stores relevant information about the product or person to which it is attached. this information can be accessed with minimal hardware, for example, a single port pin of a microcontroller. the DS1982 consists of a factory- lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (09h) plus 1kb of eprom that is user-programmable. the power to program and read the DS1982 is derived entirely from the 1-wire communication line. data is tran sferred serially via the 1-wire protocol that requires only a single data lead and a ground return. the entir e device can be programmed and then write-protected if desired. alternatively, the part may be programmed multiple times with new data being appended to, but not ove rwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provision is also incl uded for indicating that a certain pa ge or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. this page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. the 48-bit serial number th at is factory-lasered into each DS1982 provides a guaranteed unique identity that allows for absolute traceability. the durable microcan package is highly resistant to harsh environments such as dirt, mois ture, and shock. its compact button-shaped profile is self-aligning with cup-shaped recep tacles, allowing the DS1982 to be used easily by human operators or automatic equipment. accessories permit the DS1982 to be mounted on printed circ uit boards, plastic key fobs, photo-id badges, id bracelets , and many other objects. applic ations include work-in-progress tracking, electronic travelers, access control, stor age of calibration constants, and debit tokens. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the DS1982. the DS1982 has three main data component s: 1) 64-bit lasered rom, 2) 1024-bit eprom, and 3) eprom status bytes. the de vice derives its power for read oper ations entirely from the 1-wire communication line by storing energy on an internal cap acitor during periods of tim e when the signal line is high and continues to operate of f of this ?parasite? power source du ring the low times of the 1-wire line until it returns high to re plenish the parasite (capacitor) s upply. during programming, 1-wire communication occurs at normal volta ge levels and then is pulsed momentarily to the programming voltage to cause the selected eprom bits to be pr ogrammed. the 1-wire line must be able to provide 12 volts and 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltages are present on the 1-wire line a special high voltage detect circuit within the DS1982 generates an internal logic signal to indicate this condition. the hierarchical structure of the 1- wire protocol is shown in figure 2. the bus master must first provide one of the four rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom. th ese commands operate on the 64-bit lasered rom portion of each device and can si ngulate a specific device if many are present on the 1-wire line as well as indicate to the bus master how many and what types of devices are present. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functi ons that operate on the eprom portions of the DS1982 become accessible and the bus master may issu e any one of the five memory function commands specific to the DS1982 to read or pr ogram the various data fields. the protocol for these memory function commands is described in figure 6. all data is read and written least significant bit first.
DS1982 3 of 24 64-bit lasered rom each DS1982 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits (see figure 3). the 64-bit rom and rom function cont rol section allow the DS1982 to operate as a 1-wire device and follow the 1-wire protocol detailed in the section ?1-wire bus system.? the memory functions required to read and program the eprom sections of th e DS1982 are not accessible until the rom function protocol has been satisfied. this pr otocol is described in the rom func tions flow chart (figure 9). the 1-wire bus master must first pr ovide one of four rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom function sequence has been successfully executed, the bus master may then provide any one of the memory function commands specific to the DS1982 (figure 6). the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the maxim 1-wire cyclic redunda ncy check is available in the book of ds19xx i button standards. the shift register acting as the crc accumulator is initialized to 0. then starting with the least significant bit of the family code, 1 bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bi ts of crc should re turn the shift register to all 0s .
DS1982 page 4 of 24 DS1982 block diagram figure 1
DS1982 page 5 of 24 hierarchical structur e for 1-wire protocol figure 2 64-bit lasered rom figure 3 8-bit crc code 48- bit serial number 8- bit family code (09h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 bus master other devices ds 1982 command available data field level: commands: affected: read rom 64-bit rom match rom 64-bit rom search rom 64-bit rom skip rom n/a write memory 1024-bit eprom write status byte eprom status bytes read memory 1024-bit eprom read status byte eprom status bytes read data/generate 1024-bit eprom 8-bit crc 1-wire rom function commands (see figure 9) DS1982-specific memory function commands ( see figure 6 )
DS1982 page 6 of 24 1024-bit eprom the memory map in figure 5 shows the 1024-bit epro m section of the DS1982 that is configured as four pages of 32 bytes eac h. the 8-bit scratchpad is an additional register th at acts as a buffer when programming the memory. data is first written to th e scratchpad and then veri fied by reading an 8-bit crc from the DS1982 that confirms proper receipt of the data. if the buffer contents are correct, a programming voltage should be applied and the byte of data will be written into the selected address in memory. this process ensures data integrity when programming the memory. the details for reading and programming the 1024-bit eprom portion of the DS1982 are given in the "memory function commands" section. eprom status bytes in addition to the 1024 bits of data memory the DS1982 provides 64 bits of status memory accessible with separate commands. the eprom status bytes can be read or programmed to indicate various condi tions to the software interrogating the DS1982. the first byt e of the eprom status memory c ontains the write-protect page bits that inhibit programming of the corresponding page in the 1024- bit main memory area if the appropriate write protection bit is programmed. once a bit has been programmed in the write-protect page byte, the entire 32-byte page that corresponds to that bit can no longer be a ltered but may still be read. the next 4 bytes of the eprom status memory contai n the page address redire ction bytes that indicate if one or more of the pages of data in the 1024-bit eprom section have been i nvalidated and redirected to the page address contained in the appropriate redirection byte. th e hardware of the DS1982 makes no decisions based on the contents of the page address redirection bytes. these ad ditional bytes of status eprom allow for the redirection of an entire page to another page address, indica ting that the data in the original page is no longer consid ered relevant or valid. with epro m technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space permitting, an entire page of data can be redirected to another page w ithin the DS1982 by wr iting the one?s complement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the user?s software to ma ke a ?data patch? to the eprom by indicating that a particular page or pages should be replaced with those indicated in the page address redirection bytes. if a page address redirection byte has a ffh value, th e data in the main memory that corresponds to that page is valid. if a page address redirection byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one?s complement of the page address indicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. the details for readi ng and programming the ep rom status memory portion of the DS1982 are given in the memory function commands section.
DS1982 page 7 of 24 memory function commands the ?memory function flow chart? (figure 6) de scribes the protocols ne cessary for accessing the various data fields within the DS1982. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpre t the commands issued by the bus master and create the correct control signals within the device. a 3-byte protocol is issued by the bus master. it is comprised of a command byte to determine the type of opera tion and 2 address bytes to determine the specific starting byte location within a data field. the comma nd byte indicates if the device is to be read or written. writing data involves not only issuing the correct comma nd sequence but also providing a 12- volt programming voltage at the appropr iate times. to execute a write se quence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the star ting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. al l bits transferred to the DS1982 a nd received back by the bus master are sent least significant bit first. DS1982 memory map figure 5 page 0 32 bytes page 1 32 bytes page 2 32 bytes page 3 32 bytes eprom status bytes address: 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h (msb) (lsb) bit 0 write protect page 0 bit 1 write protect page 1 bit 2 write protect page 2 bit 3 write protect page 3 bit 4-7 bitmap of used pages (reserved for tmex) 8-bit scratchpad 1024-bit eprom starting address 0000h 00 2 0 h 0040h 0060h
DS1982 page 8 of 24 memory function flow chart figure 6
DS1982 page 9 of 24 memory function flow chart (cont?d) figure 6
DS1982 page 10 of 24 memory function flow chart (cont?d) figure 6
DS1982 page 11 of 24 read memory [f0h] the read memory command is used to read data from the 1024-bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data fiel d. an 8?bit crc of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the co rrect command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc recei ved by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the initial address and continuing until the end of the 1024-bit data fiel d is reached or until a reset puls e is issued. if reading occurs through the end of memory space, the bus master ma y issue eight additional read time slots and the DS1982 will respond with an 8-bit crc of all data bytes read from the initial starting byte through the last byte of memory. after the crc is received by the bus master, any subsequent read time slots will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the end of memory will not have the 8-bit crc available. typically a 16-bit crc would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see book of ds19xx i button standards, chapter 7 for the recommende d file structure to be used with the 1-wire environment.) if crc values are imbedded within the data, a reset pulse ma y be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data fr om the eprom status data field. the bus master follows the command byte with a two-byte addre ss (ta1=(t7:t0), ta2=(t15: t8)) that indicates a starting byte location w ithin the data field. an 8?bit crc of the command byte and address bytes is computed by the DS1982 and read back by the bus mast er to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the supplied address and continuing until the end of the eprom status data fi eld is reached. at that point the bus master will receive an 8-bit crc that is the re sult of shifting into the crc generato r all of the data bytes from the initial starting byte through th e final factory-programmed byte that contains the 00h value. this feature is provided since the eprom status information may change over time making it impossible to program the data once and include an accompanyi ng crc that will always be valid. therefore, the read status command supplies an 8-bit crc that is ba sed on and always is cons istent with the current data stored in the epro m status data field. after the 8-bit crc is read, the bus master will recei ve logical 1s from the DS1982 until a reset pulse is issued. the read status command sequence can be ex ited at any point by issuing a reset pulse. read data/generate 8-bit crc [c3h] the read data/generate 8-bit crc command is used to read data from the 1024-bit eprom memory field. the bus master follows the command byte with a two-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte loca tion within the data field. an 8-bit crc of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the DS1982 starting at the
DS1982 page 12 of 24 initial address and continuing until th e end of a 32-byte page is reached. at that point the bus master will send eight additional read time slots and receive an 8-bit crc that is th e result of shifting into the crc generator all of the data bytes from the initial starti ng byte to the last byte of the current page. once the 8-bit crc has been received, data is again read from the 1024-bit eprom data field starting at the next page. this sequence will continue until the fina l page and its accompanying crc are read by the bus master. thus each page of data can be considered to be 33 bytes long, the 32 bytes of user-programmed eprom data and an 8-bit crc that gets genera ted automatically at the end of each page. this type of read differs from the read memory command that simply reads each page until the end of address space is reached. the read memory command only generates an 8-bit crc at the end of memory space that often might be ignored, since in many app lications the user would store a 16-bit crc with the data itself in each page of the 1024-bit eprom data field at the time the page was programmed. the read data/generate 8-bit crc command provides an alte rnate read capability for applications that are ?bit-oriented? rather th an ?page-oriented? where the 1024-bit epro m information may change over time within a page boundary, making it impossible to progr am the page once and include an accompanying crc that will always be valid. therefore, the read data/generate 8-bit crc command concludes each page with the DS1982 generating and supplying an 8- bit crc that is based on and therefore is always consistent with the current data stored in each pa ge of the 1024-bit eprom data field. after the 8-bit crc of the last page is read, the bus master will receive logical 1s fr om the DS1982 until a reset pulse is issued. the read data/generate 8-bit crc command seque nce can be exited at any point by issuing a reset pulse. write memory [0fh] the write memory command is used to program th e 1024?bit eprom data field. the bus master will follow the command byte with a two byte starting a ddress (ta1=(t7:t0), ta2=(t15:t8)) and a byte of data (d7:d0). an 8-bit crc of the command byte, address bytes, and data byte is computed by the DS1982 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. the highest starting address within the DS1982 is 007fh. if the bus master sends a starting address higher than this, the nine most signi ficant address bits are set to 0 by the internal circuitry of the chip. this will result in a mismatch between the crc calculated by the DS1982 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a reset pulse must be i ssued and the entir e sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 ? s) is issued by the bus master. prio r to programming, the entire unprogrammed 1024-bit eprom data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bi t in the selected byte of the 1024?bit eprom will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 ? s programming pulse is ap plied and the data line returns to a 5-volt level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the DS1982 responds with the data from the selected eprom address sent least significant bit first. this byte contains the logical and of all bytes written to this eprom data addre ss. if the eprom data byte contains 1s in bit positions where the byte issued by the master c ontains 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS1982 eprom data byte contains 0s in the same bit positions as the data byte, the program ming was successful and the DS1982 will automatically increment its address counter to select the next byte in the 1024-bit eprom data field. the least
DS1982 page 13 of 24 significant byte of the new 2-byte address will also be loaded into the 8-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the DS1982 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the lsb of the current address, and th e result is an 8-bit crc of the new data byte and the lsb of the new address. after s upplying the data byte, the bu s master will read this 8-bit crc from the DS1982 with eight read time slots to confirm that the address incremented properly and the data byte was received correc tly. if the crc is incorrect, a rese t pulse must be issued and the write memory command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byt e in memory will be programmed. note that the initial pass through th e write memory flow chart will generate an 8-bit crc value that is the result of shifting the command byt e into the crc generator, followed by the 2 address bytes, and finally the data byte. subsequent passes through the write memory flow chart due to the DS1982 automatically incrementing its address counter will genera te an 8-bit crc that is the result of loading (not shifting) the lsb of the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit crc calculated by the bus master agrees with the 8-bit crc calculated by the DS1982. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorre ct programming could occur within the DS1982. also note that the DS1982 will always increm ent its internal address counter af ter the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master; therefore if the eprom data byte does not match the supplied data byte but the master conti nues with the write memory command, incorrect programming could occur within the DS1982. the write memory command sequence can be exited at any point by issu ing a reset pulse. write status [55h] the write status command is used to program the ep rom status data field. th e bus master will follow the command byte with a 2-byte star ting address (ta1=(t7:t0), ta2=(t15: t8)) and a byte of status data (d7:d0). an 8-bit crc of the command byte, addr ess bytes, and data byte is computed by the DS1982 and read back by the bus master to confirm that the correct command word, st arting address, and data byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the en tire sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 ? s) is issued by the bus master. prior to programming, the first 7 bytes of the eprom status data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the select ed byte of the eprom status data field will be programmed to a logical 0 after th e programming pulse has been appl ied at that byte location. the 8 th byte of the eprom status byte data field is factory-programmed to contain 00h. after the 480 ? s programming pulse is ap plied and the data line returns to a 5-volt level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the DS1982 responds with the data from the selected eprom status address sent least signifi cant bit first. this byte contains the logical and of all bytes written to this eprom status byte address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the DS1982 eprom status byte
DS1982 page 14 of 24 contains 0s in the same bit posit ions as the data byte, the programming was successful and the DS1982 will automatically increment its address counter to se lect the next byte in the eprom status data field. the least significant byte of the new 2-byte address will also be loaded into the 8-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the DS1982 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the ls b of the current address and the resu lt is an 8-bit crc of the new data byte and the lsb of the new address. after supplying th e data byte, the bus master will read this 8-bit crc from the DS1982 with eight read time slots to c onfirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write status command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byt e in memory will be programmed. note that the initial pass through the write status fl ow chart will generate an 8-bit crc value that is the result of shifting the command byte into the crc gene rator, followed by the 2 ad dress bytes, and finally the data byte. subsequent passes through the write status flow chart due to the DS1982 automatically incrementing its address counter will generate an 8-bit crc that is the result of loading ( not shifting) the lsb of the new (incremented) addre ss into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the DS1982) is made entirely by the bus master, since the DS1982 will not be able to determine if the 8-bit crc calculated by the bus master agrees with the 8-bit crc calculated by the DS1982. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorre ct programming could occur within the DS1982. also note that the DS1982 will always increm ent its internal address counter af ter the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master, therefore if the eprom data byte does not match the supplied data byte but the master continue s with the write status command, in correct programming could occur within the DS1982. the write status command sequen ce can be ended at any point by issuing a reset pulse. 1-wire bus system the 1-wire bus is a system which has a single bus ma ster and one or more slaves. in all instances, the DS1982 is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transacti on sequence, and 1-wire signaling (signal type and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling e dge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1-wire bus has only a si ngle line by definition; it is important that each devi ce on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain connection or 3- state outputs. the DS1982 is an open dr ain part with an internal circuit equivalent to that shown in figure 7. the bus master can be the same equivalent ci rcuit. if a bidirectional pin is not available, separa te output and input pins can be tied together. the bus master requires a pullup resistor at the ma ster end of the bus, with the bus master circuit equivalent to the one shown in figures 8a a nd 8b. the value of the pullup resistor should be approximately 5 k ?? for short line lengths.
DS1982 page 15 of 24 a multidrop bus consists of a 1-wire bus with multip le slaves attached. the 1-wire bus has a maximum data rate of 16.3kbps. if the bus master is also re quired to perform programmi ng of the eprom portions of the DS1982, a programming supply cap able of delivering up to 10 mi lliamps at 12 volts for 480 ? s is required. the idle state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transac tion is to resume. if this does not occur and the bus is left low for more than 120 ? s, one or more of the device s on the bus may be reset. transaction sequence the sequence for accessing the DS1982 via the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the DS1982 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the DS1982?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can be used onl y if there is a single DS1982 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). match rom [55h] the match rom command, followed by a 64?bit rom seque nce, allows the bus master to address a specific DS1982 on a multidrop bus. only the DS1982 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
DS1982 page 16 of 24 DS1982 equivalent circuit figure 7 bus master circuit figure 8
DS1982 page 17 of 24 rom functions flow chart figure 9
DS1982 page 18 of 24 skip rom [cch] this command can save time in a single-drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom c ode. if more than one slave is present on the bus and a read command is issued following the skip ro m command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pull?downs will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search ro m command allows the bus master to use a process of elimination to identify the 64 -bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, thr ee-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be iden tified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discu ssion of a rom search, including an actual example. 1-wire signaling the DS1982 requires strict protocols to ensure data integrity. the prot ocol consists of five types of signaling on one line: reset sequen ce with reset pulse and presence pu lse, write 0, write 1, read data and program pulse. all these signals except pres ence pulse are initiated by the bus master. the initialization sequence required to begin any comm unication with the DS1982 is shown in figure 10. a reset pulse followed by a presence pulse indicate s the DS1982 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 ? s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the 1-wire line, the DS1982 waits (t pdh , 15-60 ? s) and then transmits the presence pulse (t pdl , 60-240 ? s). read/write time slots the definitions of write and read time slots are illu strated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the DS1982 to the master by triggering a delay circuit in th e DS1982. during write time slots, the delay circuit determines when the DS1982 will sample the data line. for a read data time slot, if a 0 is to be tr ansmitted, the delay circuit determines how long the DS1982 will hold the data line low overriding the 1 generated by the master. if the data bit is a 1, the device will l eave the read data time slot unchanged . program pulse to copy data from the 8-bit scratchpad to the ep rom data or status memo ry, a program pulse of 12 volts is applied to the data line after the bus master ha s confirmed that the crc for the current byte is correct. during programming, the bus master controls th e transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the DS1982. this programming voltage (figure 12) should be applied for 480 ? s, after which the bus master returns the data line to an idle high state controlled by the pullup resistor. note that due to the high voltage programming requirements for any 1-wire eprom device, it is not possible to multidrop non-eprom based 1-wire devices with the DS1982 during programming. an internal diode with in the non-eprom based 1-wire devices will attempt to clamp the data line at approximately 8 volts and could potentiall y damage these devices.
DS1982 page 19 of 24 crc generation the DS1982 has an 8-bit crc stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bi t rom and compare it to th e value stored within the DS1982 to determine if the rom data has been rece ived error-free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. under certain conditions, the DS1982 also generate s an 8-bit crc value using the same polynomial function shown above and provides th is value to the bus master to validate the transf er of command, address, and data bytes from the bus master to the DS1982. the memory functi on flow chart of figure 6 indicates that the DS1982 computes an 8-bit crc for the command, a ddress, and data bytes received for the write memory and the write status commands and then outputs this value to the bus master to confirm proper transfer. similarly the DS1982 com putes an 8?bit crc for the command and address bytes received from the bus master for the read me mory, read status, and read data/generate 8-bit crc commands to confirm that these bytes have been received correctly. the crc generator on the DS1982 is also used to provide verifi cation of error-free data transfer as each page of data from the 1024- bit eprom is sent to the bus master during a read data/generate 8-bit crc command, and for the 8 bytes of information in the status memory field. in each case where a crc is used for data transfer validation, the bus master must calculate a crc value using the polynomial function given above and compar e the calculated value to either the 8-bit crc value stored in the 64-bit rom por tion of the DS1982 (for rom reads) or the 8-bit crc value computed within the DS1982. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry on the DS1982 that prevents a command sequence from proceeding if the crc stored in or calculated by the DS1982 does not match the value generated by the bus master. proper us e of the crc as outlined in the flow chart of figure 6 can result in a communication channel with a very high level of integrity. for more details on generating crc values including example implementations in both hard ware and software, see the book of ds19xx i button standards. initialization procedure ?r eset and prese nce pulses? figure 10 480 ? s ? t rstl < * 480 ? s ? t rsth < ? (includes recovery time) 15 ? s ? t pdh < 60 ? s 60 ? s ? t pdl < 240 ? s * in order not to mask interrupt signali ng by other devices on the 1-wire bus, t rstl + t r should always be less than 960 ? s . resistor master DS1982 master t x "reset pulse" master r x "reset pulse"
DS1982 page 20 of 24 read/write timing diagram figure 11 write-1 time slot 60 ? s ? t slot < 120 ? s 1 ? s ? t low1 < 15 ? s 1 ? s ? t rec < ? write-0 time slot 60 ? s ? t low0 < t slot < 120 ? s 1 ? s ? t rec < ? resistor master DS1982
DS1982 page 21 of 24 read-data time slot 60 ? s ? t slot < 120 ? s 1 ? s ? t lowr < 15 ? s 0 ? t release < 45 ? s 1 ? s ? t rec < ? t rdv = 15 ? s t su < 1 ? s program pulse timing diagram figure 12 resistor master DS1982
DS1982 page 22 of 24 absolute maxi mum ratings* voltage on any pin relative to ground ?0.5v to +12.0v operating temperature ?40c to +85c storage temperature ?55c to +125c ? this is a stress rating only and functional operati on of the device at these or any other conditions outside those indicated in the ope ration sections of th is specification is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40 ? c to +85 ? c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 6 logic 0 v il -0.3 +0.8 v 1, 11 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 ? a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v capacitance (t a = 25 ? c) parameter symbol min typ max units notes data (1-wire) c in/out 800 pf 9 ac electrical characteristics (v pup =2.8v to 6.0v; -40 ? c to +85 ? c) parameter symbol min typ max units notes time slot t slot 60 120 ? s write 1 low time t low1 1 15 ? s write 0 low time t low0 60 120 ? s read data valid t rdv exactly 15 ? s release time t release 0 15 45 ? s read data setup t su 1 ? s 5 recovery time t rec 1 ? s reset time high t rsth 480 ? s 4 reset time low t rstl 480 ? s presence detect high t pdhigh 15 60 ? s presence detect low t pdlow 60 240 ? s delay to program t dp 5 ? s 10 delay to verify t dv 5 ? s 10 program pulse width t pp 480 5000 ? s 10,12 program voltage rise time t rp 0.5 5.0 ? s 10 program voltage fall time t fp 0.5 5.0 ? s 10
DS1982 page 23 of 24 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 ? s of this falling edge a nd will remain valid for 14 ? s minimum. (15 ? s total from falling edge on 1-wire bus.) 6. v ih is a function of the external pul lup resistor and the pullup voltage. 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5 k ? pullup to v cc and a maximum time slot of 120 ? s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? resistor is used to pull up the data line to v cc , 5 ms after power has been applied the parasite capacitance will not affect normal communications. 10. maximum 1-wire voltage for programming paramete rs is 11.5v to 12.0v; temp erature range is -40c to +50c. 11. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 12. the accumulative duration of the programming pul ses for each address must not exceed 5 ms.
DS1982 24 of 24 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 7/08 updated the f3 microcan and f5 microcan face brands with the latest per pcn h020201. 1 8/09 added plus signs (+) to the ordering information to reflect the conversion to a lead-free product. deleted the ul bullet from the features section. 1

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